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OR3C80 Datasheet(PDF) 136 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 136 Page - Agere Systems |
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136 / 210 page ![]() 136 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 61. Master Serial Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. * Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge. Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN. 5-4532(F) Figure 83. Master Serial Configuration Mode Timing Diagram Parameter Symbol Min Max Unit DIN Setup Time* TS 60.00 — ns DIN Hold Time TH 0.00 — ns CCLK Frequency (M3 = 0) FC 5.00 16.67 MHz CCLK Frequency (M3 = 1) FC 0.63 2.08 MHz CCLK to DOUT Delay TD —5.00 ns DIN CCLK DOUT TS TH BIT N TD BIT N |
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