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OR3C80 Datasheet(PDF) 140 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 140 Page - Agere Systems |
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140 / 210 page  140 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 65. Slave Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. Note: Daisy-chaining of FPGAs is not supported in this mode. 5-2848(F) Figure 87. Slave Parallel Configuration Mode Timing Diagram Parameter Symbol Min Max Unit CS0 , CS1, WR Setup Time TS1 40.00 — ns CS0 , CS1, WR Hold Time TH1 20.00 — ns D[7:0] Setup Time: 3Cxx 3Txxx TS2 20.00 7.00 — — ns ns D[7:0] Hold Time TH2 0.00 — ns CCLK High Time: 3Cxx 3Txxx TCH 20.00 7.00 — — ns ns CCLK Low Time: 3Cxx 3Txxx TCL 20.00 7.00 — — ns ns CCLK Frequency: 3Cxx 3Txxx FC — — 25.00 66.00 MHz MHz TS1 TS2 TH2 CS1 CCLK D[7:0] CS0 WR TCL TCH TH1 |
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