OR3C80 datasheet(139/210 Pages) AGERE

139 / 210 page

Lucent Technologies Inc.

139

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 64. Slave Serial Configuration Mode Timing Characteristics

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.

5-4535(F).

Figure 86. Slave Serial Configuration Mode Timing Diagram

Parameter

Symbol

Min

Max

Unit

DIN Setup Time:

3Cxx

3Txxx

20.00

10.50

—

DIN Hold Time

0.00

—

CCLK High Time:

3Cxx

3Txxx

TCH

20.00

7.00

—

CCLK Low Time:

3Cxx

3Txxx

TCL

20.00

7.00

—

CCLK Frequency:

3Cxx

3Txxx

—

25.00

66.00

MHz

CCLK to DOUT

—

20.00

DIN

CCLK

DOUT

TCL

TCH

BIT N

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