OR3C80 datasheet(138/210 Pages) AGERE

138 / 210 page

138

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 63. Asynchronous Peripheral Configuration Mode Timing Characteristics

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

* This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.

Notes:

Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0].

D[6:0] timing is the same as the write data portion of the D7 waveform because D[6:0] are not enabled by RD.

5-4533(F)

Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram

Parameter

Symbol

Min

Max

Unit

WR, CS0, and CS1 Pulse Width

TWR

50.00

—

D[7:0] Setup Time:

3Cxx

3Txxx

20.00

10.50

—

D[7:0] Hold Time

0.00

—

RDY Delay

TRDY

—

40.00

RDY Low

1.00

8.00

CCLK Periods

Earliest WR After RDY Goes High*

TWR2

0.00

—

RD to D7 Enable/Disable

TDEN

—

40.00

CCLK to DOUT

—5.00

CS1

CCLK

DOUT

CS0

RDY

TWR

TRDY

PREVIOUS BYTE

TWR2

WRITE DATA

TDEN

OR3C80 Datasheet(PDF) 138 Page - Agere Systems

OR3C80 Datasheet(HTML) 138 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL