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OR3C80 Datasheet(PDF) 142 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 142 Page - Agere Systems |
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142 / 210 page  142 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Readback Timing Table 66. Readback Timing Characteristics OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. 5-4536(F) Figure 88. Readback Timing Diagram Parameter Symbol Min Max Unit RD_CFG to CCLK Setup Time TS 50.00 — ns RD_CFG High Width to Abort Readback TRBA 2 — CCLK cycles CCLK Low Time TCL 40.00 — ns CCLK High Time TCH 40.00 — ns CCLK Frequency FC — 12.50 MHz CCLK to RD_DATA Delay TD — 40.00 ns TD TCH CCLK RD_DATA TS TCL RD_CFG BIT 0 BIT 1 BIT 0 TRBA |
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