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OR3C80 Datasheet(PDF) 129 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 129 Page - Agere Systems |
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129 / 210 page  Lucent Technologies Inc. 129 Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued) OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. Notes: The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry. The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input. 5-4847(F).b Figure 79. Input to ExpressCLK Setup/Hold Time Description (TJ = 85 °C, VDD = min) Device Speed Unit -4 -5 -6 -7 Min Max MinMax MinMax MinMax Input to ECLK Hold Time (corner ECLK pin) OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 — — 0.00 0.00 — — — — — — 0.00 0.00 0.00 0.00 0.00 — — — — — 0.00 0.00 0.80 0.00 0.00 — — — — — 0.00 0.00 1.10 0.00 0.00 — — — — — ns ns ns ns ns Input to ECLK Hold Time (corner ECLK pin, delayed data input) OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 — — 0.00 0.00 — — — — — — 0.00 0.00 0.00 0.00 0.00 — — — — — 0.00 0.00 0.00 0.00 0.00 — — — — — 0.00 0.00 0.00 0.00 0.00 — — — — — ns ns ns ns ns Q D CLK INPUT PIO ECLK LATCH CLKCNTRL ECLK |
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