OR3C80 datasheet(126/210 Pages) AGERE

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126

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 55. OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin)

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C; CL = 50 pF.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;

CL = 50 pF.

Notes:

Timing is without the use of the programmable clock manager (PCM).

This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the

PIO CLK input, the clock

→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not

used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used.

5-4846(F).b

Figure 77. Fast Clock to Output Delay

Description

(TJ = 85 °C, VDD = min)

Device

Speed

Unit

-4

-5

-6

-7

MinMax

Min

Max

MinMax

Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)

ECLK Middle Input Pin

→OUTPUT Pin

(Fast)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

14.68

15.30

—

11.13

11.35

11.81

12.33

13.20

—

7.94

8.01

8.18

8.36

8.68

—

6.40

6.48

6.66

6.85

7.19

ECLK Middle Input Pin

→OUTPUT Pin

(Slewlim)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

17.11

17.74

—

13.12

13.33

13.80

14.32

15.19

—

8.61

8.68

8.85

9.04

9.35

—

6.93

7.01

7.19

7.38

7.72

ECLK Middle Input Pin

→OUTPUT Pin

(Sinklim)

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

18.47

19.10

—

14.47

14.68

15.15

15.67

16.54

—

13.46

13.53

13.70

13.88

14.20

—

11.67

11.75

11.93

12.12

12.46

Additional Delay if ECLK Corner Pin

Used

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

2.10

2.14

—

1.97

1.99

2.01

2.04

2.09

—

1.82

1.92

2.12

2.33

2.63

—

1.60

1.69

1.88

2.07

2.39

OUTPUT (50 pF LOAD)

ECLK

FCLK

PIO FF

CLKCNTRL

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