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MCP3911 Datasheet(PDF) 25 Page - Microchip Technology

Part # MCP3911
Description  3.3V Two-Channel Analog Front End
PDF  72 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3911 Datasheet(HTML) 25 Page - Microchip Technology

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© 2012 Microchip Technology Inc.
DS22286A-page 25
MCP3911
4.5
OSR - Oversampling Ratio
This is the ratio of the sampling frequency to the output
data rate. OSR= DMCLK/DRCLK. The default OSR is
256, or with MCLK = 4 MHz, PRESCALE = 1, AMCLK
= 4 MHz, fS = 1 MHz, fD = 3.90625 ksps. The following
bits in the CONFIG register are used to change the
oversampling ratio (OSR).
4.6
Offset Error
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. The offset is specified in µV. The offset error
can be digitally compensated independently on each
channel through the OFFCAL registers with a 24-bit
calibration word.
The offset on the MCP3911 has a low temperature
coefficient, see typical performance curves for more
information, Figure 2-33.
4.7
Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in %
compared to the ideal transfer function defined by
Equation 5-3. The specification incorporates both PGA
and ADC gain error contributions, but not the VREF
contribution (it is measured with an external VREF).
This error varies with PGA and OSR settings. The gain
error can be digitally compensated independently on
each channel through the GAINCAL registers with a
24-bit calibration word.
The gain error on the MCP3911 has a low temperature
coefficient; for more information, see Figure 2-34.
4.8
Integral Non-Linearity Error
Integral non-linearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the end points equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
4.9
Signal-To-Noise Ratio (SNR)
For the MCP3911 ADCs, the signal-to-noise ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal),
when the input is a sinewave at a predetermined
frequency. It is measured in dB. Usually, only the
maximum signal to noise ratio is specified. The SNR
figure depends mainly on the OSR and DITHER
settings of the device.
EQUATION 4-3:
SIGNAL-TO-NOISE RATIO
4.10
Signal-To-Noise Ratio And
Distortion (SINAD)
The most important figure of merit for the analog
performance of the ADCs present on the MCP3911 is
the
Signal-to-Noise
And
Distortion
(SINAD)
specification.
Signal-to-noise and distortion ratio is similar to signal-
to-noise ratio, with the exception that you must include
the harmonics power in the noise power calculation.
The SINAD specification depends mainly on the OSR
and DITHER settings.
EQUATION 4-4:
SINAD EQUATION
The calculated combination of SNR and THD per the
following formula also yields SINAD:
EQUATION 4-5:
SINAD, THD, AND SNR
RELATIONSHIP
TABLE 4-3:
MCP3911 OVERSAMPLING
RATIO SETTINGS
CONFIG
OVER SAMPLING
RATIO
OSR
OSR<2:0>
000
32
001
64
010
128
0
1
1
256 (DEFAULT)
100
512
1
0
1
1024
1
1
0
2048
1
1
1
4096
SNR dB
()
10
SignalPower
NoisePower
----------------------------------
⎝⎠
⎛⎞
log
=
SINAD dB
()
10
SignalPower
Noise
HarmonicsPower
+
--------------------------------------------------------------------
⎝⎠
⎛⎞
log
=
SINAD dB
()
10
10
SNR
10
-----------
⎝⎠
⎛⎞
10
THD
–
10
----------------
⎝⎠
⎛⎞
+
log
=



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