MCP3911 datasheet(20/72 Pages) MICROCHIP

20 / 72 page

MCP3911

DS22286A-page 20

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mV/GAIN with

VREF=1.2V.

The maximum differential voltage is proportional to the

VREF voltage. The maximum absolute voltage, with

respect to AGND, for each CHn+/- input pin is +/-1V

with no distortion and ±2V with no breaking after con-

tinuous voltage. This maximum absolute voltage is not

proportional to the VREF voltage.

3.5

Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry (See the “Functional block diagram”). To

ensure accuracy and noise cancellation, this pin must

be connected to the same ground as DGND, preferably

with a star connection. If an analog ground plane is

available, it is recommended that this pin be tied to this

plane of the PCB. This plane should also reference all

other analog circuitry in the system.

3.6

Non-inverting Reference Input,

Internal Reference Output

(REFIN+/OUT)

This pin is the non-inverting side of the differential

voltage reference input for both ADCs or the internal

voltage reference output.

When VREFEXT=1, an external voltage reference

source can be used, the internal voltage reference is

disabled. When using an external differential voltage

reference, it should be connected to its VREF+ pin.

When using an external single-ended reference, it

should be connected to this pin.

When VREFEXT=0, the internal voltage reference is

enabled and connected to this pin through a switch.

This voltage reference has minimal drive capability and

thus needs proper buffering and bypass capacitances

(a 0.1 µF ceramic capacitor is sufficient in most cases)

if used as a voltage source.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not necessary for keeping ADC accuracy, but a minimal

0.1 µF ceramic capacitance can be connected to avoid

EMI/EMC susceptibility issues due to the antenna cre-

ated by the REFIN+/OUT pin if left floating.

3.7

Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage

reference input for both ADCs. When using an external

differential voltage reference, it should be connected to

its VREF- pin. When using an external single-ended

voltage reference, or when VREFEXT=0 (Default) and

using the internal voltage reference, this pin should be

directly connected to AGND.

3.8

Digital Ground Connection

(DGND)

DGND is the ground connection to internal digital

circuitry (See the MCP3911 Block diagram). To ensure

optimal accuracy and noise cancellation, DGND must

be connected to the same ground as AGND, preferably

with a star connection. If a digital ground plane is

available, it is recommended that this pin be tied to this

plane of the Printed Circuit Board (PCB). This plane

should also reference all other digital circuitry in the

system.

3.9

Modulator Data Output Pin for

Channel 1 and Channel 0 (MDAT1/

MDAT0)

MDAT0 and MDAT1 are the output pins for the

modulator serial bitstreams of ADC channels 0 and 1,

respectively. These pins are high impedance when

their corresponding MODOUT bit is logic low. When the

MODOUT<1:0> are enabled, the modulator bitstream

of the corresponding channel is present on the pin and

updated at the AMCLK frequency. (See Section 5.4

“Modulator Output Block” for a complete description

of the modulator outputs). These pins can be directly

connected to a MCU or DSP when a specific digital

filtering is needed.

3.10

Data Ready Output (DR)

The data ready pin indicates if a new conversion result

is ready to be read. The default state of this pin is high

when DR_HIZ=1 and is high impedance when

DR_HIZ=0 (Default). After each conversion is finished,

a logic low pulse will take place on the data ready pin

to indicate the conversion result is ready as an inter-

rupt. This pulse is synchronous with the master clock

and has a defined and constant width.

The data ready pin is independent of the SPI interface

and acts like an interrupt output. The data ready pin

state is not latched and the pulse width (and period) are

both

determined

the

MCLK

frequency,

over-sampling rate, and internal clock pre-scale

settings. The DR pulse width is equal to one DMCLK

period and the frequency of the pulses is equal to

DRCLK (see Figure 1-3).

Note:

This pin should not be left floating when

DR_HIZ bit is low; a 100 k

Ω pull-up

resistor

connected

DVDD

recommended.

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