MCP3911 datasheet(53/72 Pages) MICROCHIP

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DS22286A-page 53

MCP3911

7.1

CHANNEL REGISTERS - ADC

CHANNEL DATA OUTPUT

REGISTERS

The ADC Channel Data Output registers always con-

tain the most recent A/D conversion data for each

channel. These registers are read-only. They can be

accessed independently or linked together (with

READ<1:0> bits). These registers are latched when an

ADC read communication occurs. When a data ready

event occurs during a read communication, the most

current ADC data is also latched to avoid data corrup-

tion issues. The three bytes of each channel are

updated synchronously at a DRCLK rate. The three

bytes can be accessed separately if needed, but are

refreshed synchronously.

CHANNEL REGISTER

Name

Bits

Address

R/W

CHANNEL0

0x00

CHANNEL1

0x03

R-0

DATA_CHn

<23> (MSB)

DATA_CHn

<22>

DATA_CHn

<21>

DATA_CHn

<20>

DATA_CHn

<19>

DATA_CHn

<18>

DATA_CHn

<17>

DATA_CHn

<16>

bit 23

bit 16

R-0

DATA_CHn

<15>

DATA_CHn

<14>

DATA_CHn

<13>

DATA_CHn

<12>

DATA_CHn

<11>

DATA_CHn

<10>

DATA_CHn

<9>

DATA_CHn

<8>

bit 15

bit 8

R-0

DATA_CHn

<7>

DATA_CHn

<6>

DATA_CHn

<5>

DATA_CHn

<4>

DATA_CHn

<3>

DATA_CHn

<2>

DATA_CHn

<1>

DATA_CHn

<0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23:0

DATA_CHn: Output code from ADC Channel n. This data is post-calibration if the EN_OFFCAL or

EN_GAINCAL bits are enabled.

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