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MCP3911 Datasheet(PDF) 55 Page - Microchip Technology |
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MCP3911 Datasheet(HTML) 55 Page - Microchip Technology |
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55 / 72 page ![]() © 2012 Microchip Technology Inc. DS22286A-page 55 MCP3911 7.3 PHASE Register - Phase Configuration Register Any write to one of these two addresses (0x07 and 0x08) creates an internal reset and restart sequence. REGISTER 7-3: PHASE Register Name Bits Address Cof PHASE 16 0x07 R/W U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PHASE<11> PHASE<10> PHASE<9> PHASE<8> bit 11 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASE<7> PHASE<6> PHASE<5> PHASE<4> PHASE<3> PHASE<2> PHASE<1> PHASE<0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15:12 Unimplemented, read as ‘0’ bit 11:0 CH0 relative to CH1 phase delay PHASE<11:0>: CH0 Relative to CH1 Phase Delay bits Delay = PHASE Register’s two’s complement code/DMCLK (Default PHASE = 0). |
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