MCP3911 datasheet(34/72 Pages) MICROCHIP

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MCP3911

DS22286A-page 34

FIGURE 5-2:

MDAT Serial Outputs in

Function of the Modulator Output Code.

Since the reset and shutdown SPI commands are

asynchronous, the MDAT pins are resynchronized with

DMCLK after each time the part goes out of reset and

shutdown.

This means that the first output of MDAT, after a soft

reset or a shutdown, is always 0011 after the first

DMCLK rising edge.

The two MDAT output pins are in high impedance if the

RESET pin is low.

5.5

SINC3 + SINC1 Filter

The decimation filter present in both channels of the

MCP3911 is a cascade of two sinc filters (sinc3+sinc1):

a third order sinc filter with a decimation ratio of OSR3

followed by first order sinc filter with a decimation ratio

of OSR1 (moving average of OSR1 values). Figure 5-3

represents the decimation filter architecture.

FIGURE 5-3:

MCP3911 Decimation Filter Block Diagram.

The formula for calculating the transfer function of the

digital decimation filter and settling time of the ADC is

as follows:

EQUATION 5-1:

SINC FILTER TRANSFER FUNCTION

DMCLK

MDAT+2

MDAT+1

MDAT+0

MDAT-1

MDAT-2

COMP

AMCLK

<3>

COMP

<2>

COMP

<1>

COMP

<0>

Modulator

Output

SINC

Decimation

Filter Output

OSR3

OSR1

16 (WIDTH=0)

24 (WIDTH=1)

Decimation Filter

OSR1=1

()

- OSR

–

⎝⎠

⎛⎞

OSR

z 1

–

()

()3

---------------------------------------------

- OSR

OSR

–

⎝⎠

⎛⎞

OSR

- OSR

–

⎝⎠

⎛⎞

-----------------------------------------------------------

where

EXP 2

π jf

⋅⋅

DMCLK

⁄

()

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