MCP3911 datasheet(35/72 Pages) MICROCHIP

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DS22286A-page 35

MCP3911

EQUATION 5-2:

SETTING TIME OF THE ADC AS A FUNCTION OF DMCLK PERIODS

The SINC1 filter following the SINC3 filter is only

enabled for the high OSR settings. This SINC1 filter

provides additional rejection at a low cost with little

modification to the -3 dB bandwidth. For 24-Bit Output

mode (WIDTH = 1), the output of the sinc filter is pad-

ded on the right with least significant zeros, up to 24

bits, for any resolution less than 24 bits. For 16-Bit Out-

put modes, the output of the sinc filter is rounded to the

closest 16-bit number, in order to conserve only 16-bit

words and to minimize truncation error.

The gain of the transfer function of this filter is 1 at each

multiple of DMCLK (typically 1 MHz) so a proper anti-

aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the

converter. This anti-aliasing filter can be a simple, first-

order RC network with a sufficiently low time constant

to generate high rejection at DMCLK frequency

Any unsettled data is automatically discarded to avoid

data corruption. Each data ready pulse corresponds to

fully settled data at the output of the decimation filter.

The first data available at the output of the decimation

filter is present after the complete settling time of the fil-

ter (see Table 5-4). After the first data has been pro-

cessed, the delay between two data ready pulses is 1/

DRCLK. The data stream from input to output is

delayed by an amount equal to the settling time of the

filter (which is the group delay of the filter).

The achievable resolution, the -3 dB bandwidth and the

settling time at the output of the decimation filter (the

output of the ADC), is dependent on the OSR of each

sinc filter and is summarized with the following table:

SettlingTime DMC LKPerio ds

()

OSR

–

()

OSR

TABLE 5-4:

OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME

OSR<2:0>

OSR3

OSR1

TOTAL OSR

RESOLUTION IN

BITS (NO MISSING

CODES)

SETTLING

TIME

-3 dB BANDWIDTH

96/DMCLK

0.26*DRCLK

192/DMCLK

0.26*DRCLK

128

384/DMCLK

0.26*DRCLK

256

768/DMCLK

0.26*DRCLK

512

1536/DMCLK

0.26*DRCLK

512

1024

2048/DMCLK

0.37*DRCLK

512

2048

3072/DMCLK

0.42*DRCLK

512

4096

5120/DMCLK

0.43*DRCLK

MCP3911 Datasheet(PDF) 35 Page - Microchip Technology

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