MCP3911 datasheet(43/72 Pages) MICROCHIP

43 / 72 page

DS22286A-page 43

MCP3911

6.0

SERIAL INTERFACE

DESCRIPTION

6.1

Overview

The MCP3911 device is compatible with SPI Modes 0,0

and 1,1. Data is clocked out of the MCP3911 on the

falling edge of SCK and data is clocked into the

MCP3911 on the rising edge of SCK. In these modes,

SCK can Idle either high or low.

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI

communication is independent. When CS is high, SDO

is in high-impedance, transitions on SCK, and SDI

have no effect. Additional controls: RESET, DR and

MDAT0/1 are also provided on separate pins for

advanced communication.

The MCP3911 interface has a simple command

structure. The first byte transmitted is always the

CONTROL byte and is followed by data bytes that are

8-bits wide. Both ADCs are continuously converting

data by default and can be reset or shut down through

a CONFIG register setting.

Since each ADC data is either 16 or 24 bits (depending

on the WIDTH bits), the internal registers can be

grouped together with various configurations (through

the READ bits) in order to allow easy data retrieval within

only one communication. For device reads, the internal

address counter can be automatically incremented in

order to loop through groups of data within the register

map. The SDO will then output the data located at the

ADDRESS (A<4:0>) defined in the control byte and then

ADDRESS + 1 depending on the READ<1:0> bits,

which select the groups of registers. These groups are

defined in Section 7.1 “CHANNEL REGISTERS - ADC

Channel Data Output Registers” (Register Map).

The Data Ready pin (DR) can be used as an interrupt

for an MCU and outputs pulses when a new ADC

channel data is available. The RESET pin acts like a

Hard Reset and can reset the part to its default power-

up configuration. The MDAT0/1 pins give the modulator

outputs (see Section 5.4 “Modulator Output Block”).

6.2

Control Byte

The control byte of the MCP3911 contains two device

Address bits, A<6:5>, 5 register Address bits, A<4:0>,

and a Read/Write bit (R/W). The first byte transmitted

to the MCP3911 is always the control byte.

The MCP3911 interface is device addressable (through

A<6:5>) so that multiple MCP3911 chips can be pres-

ent on the same SPI bus with no data bus contention.

This functionality enables three-phase power metering

systems, containing three MCP3911 chips, controlled

by a single SPI bus (single CS, SCK, SDI and SDO

pins).

FIGURE 6-1:

Control Byte.

The default device address bits are ‘00’. Contact the

Microchip factory for additional device address bits. For

more information, please see the Product Identification

System section.

A read on undefined addresses will give an all zeros

output on the first, and all subsequent transmitted

bytes. A write on an undefined address will have no

effect, and also will not increment the address counter.

The register map is defined in Table 7-1.

6.3

Reading from the Device

The first data byte read is the one defined by the

address given in the CONTROL byte. After this first

byte is transmitted, if the CS pin is maintained low, the

communication continues and the address of the next

transmitted byte is determined by the status of the

READ bits in the STATUSCOM register. Multiple

looping configurations can be defined through the

READ<1:0> bits for the address increment (see

Section 6.6 “SPI MODE 0,0 – Clock Idle Low, Read/

Write Examples”).

6.4

Writing to the Device

The first data byte written is the one defined by the

address given in the control byte. Two write mode con-

figurations for the address increment can be defined

through the WRITE bit in the STATUSCOM register.

When WRITE = 1, the write communication automati-

cally increments the address for subsequent bytes. The

address of the next transmitted byte within the same

communication (CS stays logic low) is the next address

defined on the register map. At the end of the register

map, the address loops to the beginning of the writable

part of the register map (address 0x06). Writing a non-

writable register has no effect. When WRITE = 0, the

address is not incremented on the subsequent writes.

The SDO pin stays in high-impedance during a write

communication.

R/W

Read/

Write Bit

Device

Address Bits

Address

Bits

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