MCP3911 datasheet(60/72 Pages) MICROCHIP

60 / 72 page

MCP3911

DS22286A-page 60

7.7

OFFCAL_CHn REGISTERS -

DIGITAL OFFSET ERROR

CALIBRATION REGISTERS

bit 2

VREFEXT Internal Voltage Reference Shutdown Control

= Internal Voltage Reference Disabled

= Internal Voltage Reference Enabled (Default)

bit 1

CLKEXT Internal Clock selection bits

= External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power

consumption) (Default)

Crystal oscillator is enabled. A crystal must be placed between OSC1 and OSC2 pins.

bit 0

Not implemented, read as 0

OFFCAL_CHn

REGISTERS

Name

Bits

Address

Cof

OFFCAL_CH0

0x0E

R/W

OFFCAL_CH1

0x14

R/W

R/W-0

...

R/W-0

OFFCAL_CHn

<23>

OFFCAL_CHn

<22>

OFFCAL_CHn

<21>

...

OFFCAL_CHn

<3>

OFFCAL_CHn

<2>

OFFCAL_CHn

<1>

OFFCAL_CHn

<0>

bit 23

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23:0

Digital Offset calibration value for the corresponding channel CHn. This register simply is added to the

output code of the channel bit-by-bit. This register is 24-bit two's complement MSB first coding.

CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a Don't Care if

EN_OFFCAL=0 (Offset calibration disabled) but its value is not cleared by the EN_OFFCAL bit.

MCP3911 Datasheet(PDF) 60 Page - Microchip Technology

MCP3911 Datasheet(HTML) 60 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL