MCP3911 datasheet(48/72 Pages) MICROCHIP

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MCP3911

DS22286A-page 48

6.7.2

CONTINUOUS WRITE

Both ADCs are powered up with their default

configurations, and begin to output data ready pulses

immediately (RESET<1:0> and SHUTDOWN<1:0>

bits are off by default).

The default output codes for both ADCs are all zeros.

The default modulator output for both ADCs is ‘0011’

(corresponding to a theoretical zero voltage at the

inputs). The default phase is zero between the two

channels.

It is recommended to enter into ADC Reset mode for

both ADCs, just after power-up, because the desired

MCP3911 register configuration may not be the default

one, and in this case, the ADC would output undesired

data. Within the ADC Reset mode (RESET<1:0> = 11),

the user can configure the whole part with a single

communication. The write commands automatically

increment the address so that the user can start writing

the PHASE register and finish with the CONFIG

The RESET<1:0> bits are in the last byte of the

CONFIG register to allow exiting the Soft Reset mode,

and have the whole part configured and ready to run in

only one command.

6.7.3

The following register sets are defined as groups:

The following register sets are defined as types:

6.8

Situations that Reset ADC Data

Immediately after the following actions, the ADCs are

reset and automatically restarted in order to provide

proper operation:

Change in PHASE register

Change in the OSR setting

Change in the PRESCALE setting

Overwrite of the same PHASE register value

Change in the CLKEXT setting

Change in the VREFEXT setting

Change in the MODOUT setting

After these temporary resets, the ADCs go back to the

normal operation, with no need for an additional

command. The PHASE register can be used to serially

Soft Reset the ADCs, without using the RESET bits in

the Configuration register, if the same value is written

in the PHASE register.

FIGURE 6-8:

Recommended Configuration Sequence at Power-up.

TABLE 6-1:

Group

Addresses

ADC DATA CH0

0x00-0x02

ADC DATA CH1

0x03-0x05

MOD, PHASE, GAIN

0x06-0x09

CONFIG, STATUSCOM

0x0A-0x0D

OFFCAL_CH0, GAINCAL_CH0

0x0E-0x13

OFFCAL_CH1, GAINCAL_CH1

0x14-0x19

VREFCAL

0x1A

TABLE 6-2:

Type

Addresses

ADC DATA

(both channels)

0x00-0x05

CONFIGURATION

0x06-0x1A

00011010

SCK

SDI

AVDD, DVDD

11XXXXXX

CONFIG2

ADDR/W

CONFIG2

Optional RESET of both ADCs

One command for writing complete configuration (without calibration)

PHASE ADDR/W

GAIN

STATUSCOM

CONFIG

PHASE

00001110

xxxxxxxx

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