MCP3911 datasheet(57/72 Pages) MICROCHIP

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DS22286A-page 57

MCP3911

7.5

STATUSCOM Register - Status

And Communication Register

STATUSCOM

Name

Bits

Address

Cof

STATUSCOM

0x0A

R/W

R/W-0

U-0

R/W-0

R/W-1

MODOUT<1>

MODOUT<0>

—

DR_HIZ

DRMODE<1>

DRMODE<0>

DRSTATUS<1>

DRSTATUS<0>

bit 15

bit 8

R/W-1

R/W-0

R/W-1

R/W-0

U-0

READ<1>

READ<0>

WRITE

WIDTH<1>

WIDTH<0>

EN_OFFCAL

EN_GAINCAL

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15:14

MODOUT<1:0>: Modulator Output Setting for MDAT pins

= Both CH0 and CH1 modulator outputs are present on MDAT1 and MDAT0 pins, both SINC fil-

ters are off, no data ready pulse is present

= CH1 ADC Modulator output present on MDAT1 pin, SINC filter on channel 1 is off, data ready

pulse from channel 1 is not present on DR pin

= CH0 ADC Modulator output present on MDAT0 pin, SINC filter on channel 0 is off, data ready

pulse from channel 0 is not present on DR pin

= No Modulator output is enabled, SINC filters are on, data readys are present on DR pin for both

channels (DEFAULT)

bit 13

Unimplemented, read as 0

bit 12

DR_HIZ: Data Ready Pin Inactive State Control

= The DR pin state is a logic high when data is NOT ready

= The DR pin state is high impedance when data is NOT ready(DEFAULT)

bit 11:10

DRMODE<1:0>: Data Ready Pin (DR) mode configuration bits

= Both Data Ready pulses from CH0 and CH1 are output on DR pin

= Data Ready pulses from CH1 ADC are output on DR pin. Data ready pulses from CH0 are not

present on the DR pin.

= Data Ready pulses from CH0 ADC are output on DR pin. Data ready pulses from CH1 are not

present on the DR pin.

= Data Ready pulses from the lagging ADC between the two are output on DR pin. The lagging

ADC depends on the PHASE register and on the OSR. (DEFAULT)

bit 9:8

DRSTATUS<1:0>: Data Ready Status

= ADC Channel 1 and Channel 0 data not ready (DEFAULT)

= ADC Channel 1 data not ready, ADC Channel 0 data ready

= ADC Channel 0 data not ready, ADC Channel 1 data ready

= ADC Channel 1 and Channel 0 data ready

bit 7:6

READ<1:0>: Address Loop Setting

= Address counter incremented, cycle through entire register set

= Address counter loops on register types (DEFAULT)

= Address counter loops on register groups

= Address not incremented, continually read single register

bit 5

WRITE: Address Loop Setting for Write mode

= Address counter loops on entire register map (DEFAULT)

= Address not incremented, continually write same single register

MCP3911 Datasheet(PDF) 57 Page - Microchip Technology

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