S25FS256S datasheet(129/154 Pages) SPANSION

129 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

129

Da ta

Shee t

(Prelim i nar y )

10.8.9

PPB Lock Bit Write (PLBWR A6h)

The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR

command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by

the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.

CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the

PLBWR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR

operation is initiated. While the PLBWR operation is in progress, the Status Register may still be read to

check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed

PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed, the Write

Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.

Figure 10.68 PPB Lock Bit Write Command Sequence

10.8.10

Password Read (PASSRD E7h)

The correct password value may be read only after it is programmed and before the Password mode has

been selected by programming the Password Protection mode bit to 0 in the ASP Register (ASP[2]). After the

Password Protection mode is selected the password is no longer readable, the PASSRD command will

output undefined data.

The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO,

least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK frequency by

the falling edge of the SCK signal. It is possible to read the Password continuously by providing multiples of

64 clock cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz.

Figure 10.69 Password Read Command Sequence

CS#

SCK

Phase

Instruction

CS#

SCK

Phase

Instruction

Data1

DataN

S25FS256S Datasheet(PDF) 129 Page - SPANSION