S25FS256S datasheet(131/154 Pages) SPANSION

131 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

131

Da ta

Shee t

(Prelim i nar y )

10.8.12

Password Unlock (PASSU E9h)

The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the

password data bytes on SI, least significant byte first, most significant bit of each byte first. The password is

sixty-four (64) bits in length.

CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the

PASSU command is not executed. As soon as CS# is driven to the logic high state, the self-timed PASSU

operation is initiated. While the PASSU operation is in progress, the Status Register may be read to check the

value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed PASSU

cycle, and is a 0 when it is completed.

If the PASSU command supplied password does not match the hidden password in the Password Register,

an error is reported by setting the P_ERR bit to 1. The WIP bit of the Status Register also remains set to 1. It

is necessary to use the CLSR command to clear the Status Register, the RESET command to software reset

the device, or drive the RESET# input low to initiate a hardware reset, in order to return the P_ERR and WIP

bits to 0. This returns the device to standby state, ready for new commands such as a retry of the PASSU

command.

If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU

command is 133 MHz.

Figure 10.71 Password Unlock Command Sequence

CS#

SCK

Phase

Instruction

Input Password Low Byte

Input Password High Byte

S25FS256S Datasheet(PDF) 131 Page - SPANSION