S25FS256S datasheet(125/154 Pages) SPANSION

125 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

125

Da ta

Shee t

(Prelim i nar y )

10.8.3

DYB Read (DYBRD FAh or 4DYBRD E0h)

The instruction is latched into SI by the rising edge of the SCK signal. The instruction is followed by the 24 or

32-bit address, depending on the address length configuration CR2V[7], selecting location zero within the

desired sector. Note, the high order address bits not used by a particular density device must be zero. Then

the 8-bit DYB access register contents are shifted out on the serial output SO. Each bit is shifted out at the

SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register

continuously by providing multiples of eight clock cycles. The address of the DYB register does not increment

so this is not a means to read the entire DYB array. Each location must be read with a separate DYB Read

command. The maximum operating clock frequency for READ command is 133 MHz.

Figure 10.60 DYBRD Command Sequence

Notes:

1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FAh.

2. A = MSB of address = 31 with command E0h.

This command is also supported in QPI Mode. In QPI Mode the instruction and address is shifted in on IO0-

IO3 and returning data is shifted out on IO0-IO3.

Figure 10.61 DYBRD QPI Mode Command Sequence

Notes:

1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FAh.

2. A = MSB of address = 31 with command E0h.

CS#

SCK

Phase

Instruction

Address

Repeat Register

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

A-3

A-2

A-1

Instruction

Address

Output DYBAR

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