S25FS256S datasheet(124/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

10.8.2

ASP Program (ASPP 2Fh)

Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN)

command must be issued. After the Write Enable (WREN) command has been decoded, the device will set

the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data

bytes on SI, least significant byte first. The ASP Register is two data bytes in length.

The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same

manner as any other programming operation.

CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the

ASPP command is not executed. As soon as CS# is driven to the logic high state, the self-timed ASPP

operation is initiated. While the ASPP operation is in progress, the Status Register may be read to check the

value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ASPP

operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable Latch

(WEL) is set to a 0.

Figure 10.59 ASPP Command

CS#

SCK

Phase

Instruction

Input ASPR Low Byte

Input ASPR High Byte

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