AMD-K6 datasheet(204/346 Pages) AMD

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Cache Organization

Chapter 8

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Cache Snooping

Table 32 shows the conditions under which snooping occurs in

the AMD-K6 processor and the resources that are snooped.

Table 32. Snoop Action

Type of Event

Type of Access

Snooping Action

Instruction

Cache

Data Cache

Inquire Cycle

System Logic

yes1

Internal Snoop

Instruction

Cache

Read

Miss

–

yes2

Read

Hit

–no

Data

Cache

Read

Miss

yes3

–

Read

Hit

–

Write

Miss

yes3

–

Write

Hit

–

Notes:

1. The processor’s response to an inquire cycle depends on the state of the INV input signal

and the state of the cache line as follows:

For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but

if INV is sampled asserted, the line is invalidated.

For the data cache, if INV is sampled negated, valid lines remain in or transition to the

shared state, a modified data cache line is written back before the line is marked shared

(with HITM# asserted), and invalid lines remain invalid. For the data cache, if INV is

sampled asserted, the line is marked invalid. Modified lines are written back before

invalidation.

2. If an internal snoop hits a modified line in the data cache, the line is written back and

invalidated. Then the instruction cache performs a burst read from memory.

3. If an internal snoop hits a line in the instruction cache, the instruction cache line is

invalidated and the data-cache read or write is performed from memory.

– Not applicable.

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