AMD-K6 datasheet(200/346 Pages) AMD

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182

Cache Organization

Chapter 8

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

bus, the two cache-line fills typically appear as two 32-byte

burst read cycles occurring back-to-back or, if allowed, as

pipeli ned cy c l es. Th e burs t read cy c l es do not oc cur

back-to-back (wait states occur) if the processor is not ready to

start a new cycle, if higher priority data read or write requests

exist, or if NA# (next address) was sampled negated. Wait states

can also exist between burst cycles if the processor samples

AHOLD or BOFF# asserted.

8.9

Cache States

Table 30 shows all the possible cache-line states before and

after program-generated accesses to individual cache lines. The

table includes the correspondence between MESI states and

writethrough or writeback states for lines in the data cache.

Table 30. Data Cache States for Read and Write Accesses

Type

Cache State Before

Access

Type1

Cache State After Access

MESI State

Writeback

Writethrough State

Cache

Read

Read Miss

invalid

single read

invalid

–

invalid

burst read2

(cacheable)

shared or

exclusive3

writethrough or

writeback3

Read

Hit

shared

–

shared

writethrough

exclusive

–

exclusive

writeback

modified

–

modified

writeback

Cache

Write

Write Miss

invalid

single write4

invalid

–

Write Hit

shared

cache update and

single write

shared or

exclusive3

writethrough or

writeback3

exclusive or modified

cache update

modified

writeback

Notes:

1. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read.

2. If CACHE# is driven Low and KEN# is sampled asserted.

3. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state.

4. A write cycle occurs only if the write allocate conditions as specified in “Write Allocate” on page 177 are not met.

– Not applicable or none.

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