AMD-K6 datasheet(198/346 Pages) AMD

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180

Cache Organization

Chapter 8

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

write allocations between 640 Kbytes and 1 Mbyte (000A_0000h

to 000F_FFFFh) because it is considered a non-cacheable

region of memory.

Figure 70 shows the logic flow for all the mechanisms involved

with write allocate for memory bus cycles. The left side of the

diagram (the text) describes the conditions that need to be true

in order for the value of that line to be a 1. Items 1 to 3 of the

diagram are related to general cache operation and items 4 to

11 are related to the write allocate mechanisms.

Fo r mor e inf o r m a t i o n a b out wri t e all o c a te, see the

Implementation of Write Allocate in the K86™ Processors

Application Note, order# 21326.

Figure 70. Write Allocate Logic Mechanisms and Conditions

Descriptions of the

Logic Mechanisms

and Conditions

1. CD Bit of CR0—When the cache disable (CD) bit within

control register 0 (CR0) is set to 1, the cache fill mechanism

for both reads and writes is disabled, therefore write

allocate does not occur.

2. PCD Signal—When the PCD (page cache disable) signal is

driven High, caching for that page is disabled even if KEN#

is sampled asserted, therefore write allocate does not occur.

3. CI Bit of TR12—When the cache inhibit bit of Test Register

12 is set to 1, the L1 caches are disabled, therefore write

allocate does not occur.

4. Write to a Cacheable Page (CCR)—A write allocate is

performed if the processor knows that a page is cacheable.

The CCR is used to store the page address of the last cache

fill for a read miss. See “Write to a Cacheable Page” on page

178 for a detailed description of this condition.

1) CD Bit of CR0.

Perform

Write Allocate

3) CI Bit of TR12

2) PCD Signal

4) Write to Cacheable Page (CCR)

5) Write to a Sector

8) Between 640 Kbytes and 1 Mbyte

7) Less Than Limit (WAELIM)

9) Between 15–16 Mbytes

10) Write Allocate Enable 15–16 Mbyte (WAE15M)

6) WCDE Bit

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