AMD-K6 datasheet(201/346 Pages) AMD

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Chapter 8

Cache Organization

183

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

8.10

Cache Coherency

Different ways exist to maintain coherency between the system

memory and cache memories. Inquire cycles, internal snoops,

FLUSH#, WBINVD, INVD, and line replacements all prevent

inconsistencies between memories.

Inquire Cycles

Inquire cycles are bus cycles initiated by system logic. These

inquiries ensure coherency between the caches and main

memory. In systems with multiple caching masters, system logic

maintains cache coherency by driving inquire cycles to the

processor. System logic initiates inquire cycles by asserting

AHOLD, BOFF#, or HOLD to obtain control of the address bus

and then driving EADS#, INV (optional), and an inquire

address (A[31:5]). This type of bus cycle causes the processor to

compare the tags for both its instruction and data caches with

the inquire address. If there is a hit to a shared or exclusive line

in the data cache or a valid line in the instruction cache, the

processor asserts HIT#. If the compare hits a modified line in

the data cache, the processor asserts HIT# and HITM#. If

HITM# is asserted, the processor writes the modified line back

to memory. If INV was sampled asserted with EADS#, a hit

invalidates the line. If INV was sampled negated with EADS#, a

hit leaves the line in the shared state or transitions it from the

exclusive or modified to shared state.

Internal Snooping

Internal snooping is initiated by the processor (rather than

system logic) during certain cache accesses. It is used to

maintain coherency between the L1 instruction and data

caches.

The processor automatically snoops its instruction cache during

read or write misses to its data cache, and it snoops its data

cache during read misses to its instruction cache. Table 31 on

page 185 summarizes the actions taken during this internal

snooping.

If an internal snoop hits its target, the processor does the

following:

Data cache snoop during an instruction-cache read miss—If

modified, the line in the data cache is written back to

memory. Regardless of its state, the data-cache line is

invalidated and the instruction cache performs a burst cycle

read from memory.

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