AMD-K6 datasheet(209/346 Pages) AMD

209 / 346 page

Chapter 9

Floating-Point and Multimedia Execution Units

191

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

9.2

Multimedia Execution Unit

The multimedia execution unit of the AMD-K6 processor is

designed to accelerate the performance of software written

using the industry-standard MMX instructions. Applications

that can take advantage of the MMX instructions include

graphics, video and audio compression and decompression,

speech recognition, and telephony applications.

The multimedia execution unit can execute MMX instructions

in a single processor clock. To increase performance, the

processor is designed to simultaneously decode all MMX

instructions with most other instructions.

For more information on MMX instructions, refer to AMD-K6®

Processor Multimedia Technology, order# 20726.

9.3

Floating-Point and MMX™ Instruction Compatibility

Registers

T h e eight 64-bit MMX r egister s ar e mappe d on t h e

floating-point stack. This enables backward compatibility with

all existing software. For example, the register saving event

that is performed by operating systems during task switching

requires no changes to the operating system. The same support

provided in an operating system’s interrupt 7 handler (Device

Not Available) for saving and restoring the floating-point

registers also supports saving and restoring the MMX registers.

Exceptions

There are no new exceptions defined for supporting the MMX

instructions. All exceptions that occur while decoding or

executing an MMX instruction are handled in existing

exception handlers without modification.

FERR# and IGNNE#

MMX instructions do not generate floating-point exceptions.

However, if an unmasked floating-point exception is pending,

the processor asserts FERR# at the instruction boundary of the

next floating-point instruction, MMX instruction, or WAIT

instruction.

The sampling of IGNNE# asserted only affects processor

ope rat io n during t h e e x ec ut ion of an er ro r-sensi t ive

floating-poin t instru ct io n, MMX inst ruct io n, or WAIT

instruction when the NE bit in CR0 is set to 0.

AMD-K6 Datasheet(PDF) 209 Page - Advanced Micro Devices

AMD-K6 Datasheet(HTML) 209 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL