AMD-K6 datasheet(232/346 Pages) AMD

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Test and Debug

Chapter 11

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

The states of the TAP controller are described as follows:

Test-Logic-Reset. This state represents the initial reset state of the

TAP controller and is entered when the processor samples

RESET asserted, when TRST# is asynchronously asserted, and

when TMS is sampled High for five or more consecutive clocks.

In addition, this state can be entered from the Select-IR-Scan

state. The IR is initialized with the IDCODE instruction, and

the processor’s normal operation is not affected in this state.

Capture-DR. During the SAMPLE/PRELOAD instruction, the

processor loads the BSR shift register with the current state of

every input, output, and bidirectional pin. During the EXTEST

instruction, the processor loads the BSR shift register with the

current state of every input and bidirectional pin.

Capture-IR. When the TAP controller enters the Capture-IR

state, the processor loads 01b into the two least significant bits

of the IR shift register and loads 000b into the three most

significant bits of the IR shift register.

Shift-DR. While in the Shift-DR state, the selected TDR shift

shift, the most significant bit of the TDR is loaded from the

TDI pin.

Shift-IR. While in the Shift-IR state, the IR shift register is

serially shifted toward the TDO pin. During the shift, the most

significant bit of the IR is loaded from the TDI pin.

Update-DR. During the SAMPLE/PRELOAD instruction, the BSR

output register is loaded with the contents of the BSR shift

well as those bidirectional pins defined as outputs, are driven

with their corresponding values from the BSR output register.

Update-IR. In this state, the IR output register is loaded from the

IR shift register, and the current instruction is defined by the

IR output register.

AMD-K6 Datasheet(PDF) 232 Page - Advanced Micro Devices