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AMD-K6 Datasheet(PDF) 233 Page - Advanced Micro Devices |
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AMD-K6 Datasheet(HTML) 233 Page - Advanced Micro Devices |
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233 / 346 page ![]() Chapter 11 Test and Debug 215 20695H/0—March 1998 AMD-K6® Processor Data Sheet Preliminary Information The following states have no effect on the normal or test operation of the processor other than as shown in Figure 73 on page 213: s Run-Test/Idle—This state is an idle state between scan operations. s Select-DR-Scan—This is the initial state of the test data register state transitions. s Select-IR-Scan—This is the initial state of the Instruction Register state transitions. s Exit1-DR—This state is entered to terminate the shifting process and enter the Update-DR state. s Exit1-IR—This state is entered to terminate the shifting process and enter the Update-IR state. s Pause-DR—This state is entered to temporarily stop the shifting process of a Test Data Register. s Pause-IR—This state is entered to temporarily stop the shifting process of the Instruction Register. s Exit2-DR—This state is entered in order to either terminate the shifting process and enter the Update-DR state or to resume shifting following the exit from the Pause-DR state. s Exit2-IR—This state is entered in order to either terminate the shifting process and enter the Update-IR state or to resume shifting following the exit from the Pause-IR state. 11.4 L1 Cache Inhibit Purpose The AMD-K6 processor provides a means for inhibiting the normal operation of its L1 instruction and data caches while still supporting an external Level-2 (L2) cache. This capability allows system designers to disable the L1 cache during the testing and debug of an L2 cache. If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set to 0, the processor’s L1 cache is enabled and operates as described in “Cache Organization” on page 171. If the Cache Inhibit bit is set to 1, the L1 cache is disabled and no new cache lines are allocated. Even though new allocations do not occur, valid L1 cache lines remain valid and are read by the processor when a requested address hits a cache line. In addition, the processor continues to support inquire cycles initiated by the |
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