AMD-K6 datasheet(241/346 Pages) AMD

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Chapter 12

Clock Control

223

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Clock Control

The AMD-K6 processor supports five modes of clock control.

The processor can transition between these modes to maximize

performance, to minimize power dissipation, or to provide a

balance between performance and power. (See “Power

Dissipation” on page 235 for the maximum power dissipation of

the AMD-K6 processor within the normal and reduced-power

states.)

The five clock-control states supported are as follows:

Normal State: The processor is running in Real Mode,

Virtual-8086 Mode, Protected Mode, or System Management

Mode (SMM). In this state, all clocks are running—including

the external bus clock CLK and the internal processor

clock—and the full features and functions of the processor

are available.

Halt State: This low-power state is entered following the

successful execution of the HLT instruction. During this

state, the internal processor clock is stopped.

Stop Grant State: This low-power state is entered following

the recognition of the assertion of the STPCLK# signal.

During this state, the internal processor clock is stopped.

Stop Grant Inquire State: This state is entered from the Halt

state and the Stop Grant state as the result of a

system-initiated inquire cycle.

Stop Clock State: This low-power state is entered from the

Stop Grant state when the CLK signal is stopped.

The following sections describe each of the four low-power

states. Figure 78 on page 228 illustrates the clock control state

transitions.

AMD-K6 Datasheet(PDF) 241 Page - Advanced Micro Devices