AMD-K6 datasheet(245/346 Pages) AMD

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AMD-K6 Datasheet(PDF) 245 Page - Advanced Micro Devices

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Chapter 12

Clock Control

227

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

All other input signals must remain unchanged in the Stop

Clock state.

Exit Stop Clock State

The AMD-K6 processor returns to the Stop Grant state from the

Stop Clock state after the CLK signal is started and the internal

PLL has stabilized. PLL stabilization is achieved after the CLK

signal has been running within its specification for a minimum

of 1.0 ms.

The frequency of CLK when exiting the Stop Clock state can be

different than the frequency of CLK when entering the Stop

Clock state.

The state of the BF[2:0] signals when exiting the Stop Clock

state is ignored because the BF[2:0] signals are only sampled

during the falling transition of RESET.

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