AMD-K6 datasheet(190/346 Pages) AMD

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Cache Organization

Chapter 8

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

The processor cache design takes advantage of a sectored

organization (See Figure 68). Each sector consists of 64 bytes

configured as two 32-byte cache lines. The two cache lines of a

sector share a common tag but have separate MESI (modified,

exclusive, shared, invalid) bits that track the state of each cache

line.

Instruction Cache Line

Data Cache Line

Note: Instruction-cache lines have only two coherency states (valid or invalid) rather than

the four MESI coherency states of data-cache lines. Only two states are needed for the

instruction cache because these lines are read-only.

Figure 68. Cache Sector Organization

8.1

MESI States in the Data Cache

The state of each line in the caches is tracked by the MESI bits.

The coherency of these states or MESI bits is maintained by

internal processor snoops and external inquiries by the system

logic. The following four states are defined for the data cache:

Modified—This line has been modified and is different from

main memory.

Exclusive—This line is not modified and is the same as main

memory. If this line is written to, it becomes Modified.

Shared—If a cache line is in the shared state it means that

the same line can exist in more than one cache system.

Invalid—The information in this line is not valid.

8.2

Predecode Bits

Decoding x86 instructions is particularly difficult because the

instructions vary in length, ranging from 1 to 15 bytes long.

Predecode logic supplies the predecode bits associated with

each instruction byte. The predecode bits indicate the number

Tag

Address

Cache Line 1

Byte 31 Predecode Bits

Byte 30 Predecode Bits

........

Byte 0 Predecode Bits 1 MESI Bit

Cache Line 2

Byte 31 Predecode Bits

Byte 30 Predecode Bits

........

Byte 0 Predecode Bits 1 MESI Bit

Tag

Address

Cache Line 1

Byte 31

Byte 30

........

Byte 0

2 MESI Bits

Cache Line 2

Byte 31

Byte 30

........

Byte 0

2 MESI Bits

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