AMD-K6 datasheet(193/346 Pages) AMD

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Chapter 8

Cache Organization

175

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Table 29 describes how the CACHE# signal is driven based on

writeback cycles, the CI bit of TR12, unlocked memory reads,

and the PCD signal.

Cache-Related Signals

Complete descriptions of the signals that control cacheability

and cache coherency are given on the following pages:

CACHE#—page 90

EADS#—page 94

FLUSH#—page 97

HIT#—page 98

HITM#—page 98

INV—page 102

KEN#—page 103

PCD—page 107

PWT—page 109

WB/WT#—page 116

8.4

Cache Disabling

To completely disable all cache accesses, the CD and NW bits

must be set to 1 and the cache must be completely flushed.

There are two different methods for flushing the cache. The

first method relies on the system logic and the second relies on

software.

Table 29. CACHE# Signal Generation

Writeback

Cycle

CI Bit of TR12

Unlocked

Memory Reads

PCD Signal

CACHE#

Low

High

Low

High

Low

High

Low

High

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