AMD-K6 datasheet(191/346 Pages) AMD

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Chapter 8

Cache Organization

173

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

of bytes to the start of the next x86 instruction. The predecode

bits are passed with the instruction bytes to the decoders where

they assist with parallel x86 instruction decoding. The

predecode bits use memory separate from the 32-Kbyte

instruction cache. The predecode bits are stored in an extended

instruction cache alongside each x86 instruction byte as shown

in Figure 68 on page 172.

8.3

Cache Operation

The operating modes for the caches are configured by software

using the not writethrough (NW) and cache disable (CD) bits of

control register 0 (CR0 bits 29 and 30 respectively). These bits

are used in all operating modes.

When the CD and NW bits are both set to 0, the cache is fully

enabled. This is the standard operating mode for the cache. If a

read miss occurs when the processor reads from the cache, a

line fill takes place. Write hits to the cache are updated, while

write misses and writes to shared lines cause external memory

updates.

Note: A write allocate operation can modify the behavior of write

misses to the cache. See “Write Allocate” on page 177.

When CD is set to 0 and NW is set to 1, an invalid mode of

operation exists that causes a general protection fault to occur.

When CD is set to 1 (disabled) and NW is set to 0, the cache fill

mechanism is disabled but the contents of the cache are still

valid. The processor reads from the cache and, if a read miss

occurs, no line fills take place. Write hits to the cache are

updated, while write misses and writes to shared lines cause

external memory updates.

When the CD and NW bits are both set to 1, the cache is fully

disabled. Even though the cache is disabled, the contents are

not necessarily invalid. The processor reads from the cache and,

if a read miss occurs, no line fills take place. If a write hit

occurs, the cache is updated but an external memory update

does not occur. If a data line is in the exclusive state during a

write hit, the MESI bits are changed to the modified state.

Write misses access memory directly.

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