ADAV802_15 datasheet(31/53 Pages) AD

31 / 53 page

Preliminary Technical Data

ADAV802

Rev. Pr G | Page 31 of 53

Table 32. Group Delay and Mute Register

MUTE_SRC

GRPDLY6-0

6,5,4,3,2,1,0

ADDRESS = 0001000

MUTE_SRC

Soft Mutes the Output of theSample Rate Converter

0 = No Mute

1 = Soft Mute

GRPDLY6-0

Adds delay to the Sample Rate Converter FIR filter by GRPDLY6-0 Input Samples

0000000 = No Delay

0000001 = 1 Sample Delay

0000010 = 2 Sample Delay

1111110 = 126 Sample Delay

1111111 = 127 Sample Delay

Table 33. Receiver Configuration 1 Register

NO- CLOCK

RXCLK1-0

AUTO_ DEEMPH

ERR1-0

LOCK1-0

6,5

3,2

1,0

ADDRESS = 0001001

NOCLOCK

Selects the source of the Receiver Clock when the PLL is not locked

0 = The Recovered PLL Clock is used

1 = ICLK1 is used

RXCLK1-0

Determines the oversampling ratio of the Recovered Receiver Clock

00 = RxCLK is a 128 × fS recovered clock

01 = RxCLK is a 256 × fS recovered clock

10 = RxCLK is a 512 × fS recovered clock

11 = Reserved

AUTO_DEEMPH

Automatically de-emphasizes the data from the receiver based on the

Channel Status Information

0 = Automatic De-emphasis is disabled

1 = Automatic De-emphasis is enabled

ERR1-0

Defines what action the receiver should take if the receiver detects a parity or

biphase error

00 = No action will be taken

01 = The last valid sample is held

10 = The invalid sample is replaced with zeros

11 = Reserved

LOCK1-0

Defines what action the receiver should take if the PLL loses lock.

00 = No action will be taken

01 = The last valid sample will be held

10 = Zeros will be sent out after the last valid sample

11 = Soft Mute of the last valid audio sample

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