ADAV802_15 datasheet(46/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 46 of 53

Table 76. ADC Control Register 1

AMC

HPF

PWRDWN

AND_PD

MUTER

MUTEL

PLPD

PRPD

ADDRESS = 1101110

AMC

ADC Modulator Clock

0 = ADC MCLK/2 (128 × fS)

1 = ADC MCLK/4 (64 × fS)

HPF

High Pass Filter Enable

0 = Normal

1 = HPF Enabled

PWRDWN

ADC Powerdown

0 = Normal

1 = Powerdown

ANA_PD

ADC Analog Section Powedown

0 = Normal

1 = Powedown

MUTER

Mute ADC Right Channel

0 = Normal

1 = Muted

MUTEL

Mute ADC Left Channel

0 = Normal

1 = Muted

PLPD

PGA Left Powerdown

0 = Normal

1 = Powerdown

PRPD

PGA Right Powerdown

0 = Normal

1 = Powerdown

Table 77. ADC Control Register 2

RES

BUF_PD

RES

MCD1

MCD0

ADDRESS = 1101111

BUF_PD

Reference Buffer Powerdown Control

0 = Normal

1 = Powerdown

MCD1-0

ADC Master Clock Divider

00 = Divide by 1

01 = Divide by 2

10 = Divide by 3

11 = Divide by 1

Table 78. ADC Left Volume Register

AVOLL7

AVOLL6

AVOLL5

AVOLL4

AVOLL3

AVOLL2

AVOLL1

AVOLL0

ADDRESS = 1110000

AVOLL7-0

ADC Left Channel Volume Control

1111111 = 1.0 (0dBFS)

1111110 = 0.996 (-0.00348dBFS)

1000000 = 0.5 (-6dBFS)

0111111 = 0.496 (-6.09dBFS)

0000000 = 0.0039 (-48.18dBFS)

ADAV802 Datasheet(PDF) 46 Page - Analog Devices

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