ADAV802_15 datasheet(15/53 Pages) AD

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Preliminary Technical Data

ADAV802

Rev. Pr G | Page 15 of 53

DAC SECTION

The ADAV802 has two DAC channels arranged as a stereo pair

with differential analog outputs. Each channel has its own

independently programmable attenuator, adjustable in 128 steps

of 0.375dB per step. The DAC can receive data from the

playback or auxiliary input ports, the SRC, the ADC or the DIR.

Each analog output pin sits at a dc level of VREF, and swings 1.0

Vrms for a 0dB digital input signal. A single op-amp third-order

external low-pass filter is recommended to remove high-

frequency noise present on the output pins. Note that the use of

op amps with low slew rate or low bandwidth may cause high

frequency noise and tones to fold down into the audio band;

care should be exercised in selecting these components. The

FILTD and FILTR pins should be bypassed by external

capacitors to AGND. The FILTD pin is used to reduce the noise

of the internal DAC bias circuitry, thereby reducing the DAC

output noise. The voltage at the VREF pin, FILTR can be used to

bias external op amps used to filter the output signals. For

applications where the FILTR is required to drive external op

amps which may draw more than 50µA or may have dynamic

load changes extra buffering should be used to preserve the

quality of the ADAV802 reference. The digital input data source

for the DAC can be selected from a number of available sources.

by programming the appropriate bits in the Datapath Control

source for the DAC are selected. Each DAC has an independent

volume register giving 256 steps of control with each step giving

approximately 0.375dB of attenuation. Each DAC also has a

peak level register which records the peak value of the digital

audio data. Reading the register clears the peak .

Selecting a Sample Rate

Correct operation of the DAC is dependant upon the data rate

provided to the DAC, the master clock applied to the DAC and

the selected interpolation rate. By default the DAC assumes that

the MCLK rate is 256 times the sample rate which requires an 8

times oversampling rate. This combination is suitable for

sample rates up to 48kHz. For the case of a 96kHz data rate

which has a 24.576MHz MCLK (256 × fS) associated with it the

DAC MCLK divider should be set to divide the MCLK by 2.

This will prevent the DAC engine being run too fast. To

compensate for the reduced MCLK rate the interpolator should

be selected to operate in 4 × (DAC MCLK = 128 × fS). Similar

combinations can be selected for different sample rates.

REG: 0x76

BITS 7-5

DAC

MCLK

AUXILIARY IN

PLAYBACK

DIR

ADC

REG: 0x63

BITS 5-3

DAC

INPUT

MCLK

DIVIDER

REG: 0x65

BITS 3-2

801-0007

Figure 7. Clock and data Path Control on the DAC

MULTI-BIT

SIGMA-DELTA

MODULATOR

INTERPOLATOR

DAC

TO ZERO FLAG PINS

PEAK

DETECTOR

ZERO DETECT

FROM DAC

DATAPATH

MULTIPLEXER

VOLUME/MUTE

CONTROL

TO CONTROL

REGISTERS

ANALOG

OUTPUT

801-0006

Figure 8. DAC Block Diagram

ADAV802 Datasheet(PDF) 15 Page - Analog Devices

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