ADAV802_15 datasheet(12/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 12 of 53

FUNCTIONAL DESCRIPTION

ADC SECTION

The ADAV802's ADC section is implemented using a 2nd order

multi-bit (5-bits) Sigma-Delta modulator. The modulator is

sampled at either half the ADC MCLK rate (Modulator Clock =

128 × fS) or a quarter of the ADC MCLK rate (Modulator Clock

= 64 × fS). The digital decimator consists of a Sinc^5 filter

followed by a cascade of 3 half-band FIR filters. The Sinc

decimates by a factor of 16 at 48 kHz and by 8 at 96 kHz. Each

of the half-band filters decimates by a factor of 2. Figure 3 below

shows the detail of the ADC section. The ADC can be clocked

by a number of different clock sources to control the sample

rate. MCLK selection for the ADC is set by Internal Clocking

Control Register 1 (address = 0x76). The ADC provides an

output word of up to 24 bits in resolution in 2s complement

format. The output word can be routed to the output ports, to

the sample rate converter or to the SPDIF digital transmitter.

REG: 0x76

BITS 4-2

ADC

MCLK

ADC MCLK

DIVIDER

REG: 0x6F

BITS 1-0

Figure 3. Clock Path Control on the ADC

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA which converts

the single-ended signal to a differential signal which is applied

to the analog sigma-delta modulator of the ADC. The PGA can

be programmed to amplify a signal by up to 24dB in 0.5dB

increments. Figure 4 details the structure of the PGA circuit.

Ω

4- 64 k

Ω

125

Ω

125

Ω

Modulator

CAPxN

CAPxP

External

Capacitor

(1nF NPO)

External

Capacitor

(1nF NPO)

External

Capacitor

(1nF NPO)

Ω

VREF

Figure 4. PGA Block Diagram

Analog Sigma Delta Modulator

The ADC features a 2nd order, multi-bit, Sigma-Delta modulator.

The input features two integrators in cascade followed by a flash

converter. This multi-bit output is directed to a scrambler,

followed by a DAC for loop feedback. The Flash ADC output is

also converted from "thermometer" coding to "binary" coding

for input as a 5-bit word to the decimator. Figure 5 shows the

ADC block diagram.

The ADC also features independent digital volume control for

the left and right channels. The volume control consists of 256

linear steps with each step reducing the digital output codes by

0.39%. Each channel also has a peak detector which records the

peak level of the input signal. The peak detector register is

cleared by reading it.

ADC MODCLK

MULTI-BIT

SIGMA-DELTA

MODULATOR

DECIMATOR

VOLUME

CONTROL

PEAK

DETECT

HPF

HALFBAND

FILTER

SINC^5

HALFBAND

FILTER

ADC MCLK/2

(TYP 6.144MHz)

384kHz

768kHz

192kHz

384kHz

SINC

COMPENSATION

96kHz

192kHz

48kHz

96kHz

801-0003

Figure 5. ADC Block Diagram

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