ADAV802_15 datasheet(38/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 38 of 53

Table 51. Sample Rate Converter Error Mask Register

RES

OVRL Mask

OVRR Mask

MUTE_IND MASK

ADDRESS = 0011011

OVRL Mask

Masks the OVRL from generating an interrupt

0 = The OVRL bit will not generate an interrupt

1 = The OVRL bit will generate an interrupt

OVRR Mask

Masks the OVRR from generating an interrupt

0 = The OVRR bit will not generate an interrupt

1 = The OVRR bit will generate an interrupt Reserved

MUTE_IND MASK

Masks the MUTE_IND from generating an interrupt

0 = The MUTE_IND bit will not generate an interrupt

1 = The MUTE_IND bit will generate an interrupt

Table 52. Interrupt Status Register

SRC

TxCST-

TxUB-

TxCS-

RxCS-

RxUB-

RxCS-

Rx-

Error

INT

DIFF

INT

BINT

ERROR

ADDRESS = 0011100

SRCERROR

This bit will be set if one of the sample rate converter interrupts is asserted, and the host should immediately read the

Sample Rate Converter Error register. This bit will remain high until the Interrupt Status register is read

TxCSTINT

This bit will be set if a write to the transmitter channel status buffer was made while transmitter channel status bits were

being copied from transmitter CS buffer to SPDIF Transmit buffer

TxUBINT

This bit will be set if the SPDIF Transmit buffer is empty. This bit will remain high until the Interrupt Status register is read.

TxCSINT

This bit will be set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit will remain

high until the Interrupt Status register is read

RxCSDIFF

This bit will be set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit will

remain high until read but does not generate an interupt

RxUBINT

This bit will be set if the Receiver User bit buffer has a new block or message. This bit will remain high until the Interrupt

Status register is read.

RxCSBINT

This bit will be set if a new block of channel status is read when RxBCONF3 = 0 or if the channel status has changed when

RxBCONF3 = 1. This bit will remain high until the Interrupt Status register is read.

RxERROR

This bit will be set if one of the AES3/SPDIF receiver interrupts is asserted and the host should immediately read the Receiver

Error register. This bit will remain high until the Interrupt Status register is read.

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