ADAV802_15 datasheet(19/53 Pages) AD

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Preliminary Technical Data

ADAV802

Rev. Pr G | Page 19 of 53

clock source connected directly to XIN. A 54MHz clock can

also be used if the internal clock divider is used. Both PLLs

(PLL1 and PLL2) can be programmed independently and cater

for a range of sampling rates (32/44.1/48 kHz) with selectable

system clock oversampling rates of 256 and 384. Higher

oversampling rates can also be selected by enabling the

doubling of the sampling rate to give 512 or 768 × fS ratios. Note

that this option also allows oversampling ratios of 256 or 384 at

double sample rates of 64/88.2/96 kHz. The PLL outputs can be

routed internally to act as clock sources for the other

component blocks such as the ADC, DAC etc. The outputs of

the PLLs are also available on the three SYSCLK pins. Figure 18

shows how the PLLs can be configured to provide the sampling

clocks.

XTAL

Figure 15. Crystal Connection

Table 19. PLL Frequency Selection Options

PLL

Sample Rate

MCLK Selection

(fS)

Normal fS

Double fS

32/44.1/48 kHz

256/384×fS

512/768×fS

64/88.2/96 kHz

256/384×fS

32/44.1/48 kHz

256/384×fS

512/768×fS

64/88.2/96 kHz

256/384×fS

Same as fS selected

512×fS

for PLL 2A

512×fS

The PLLs require a some external components to operate

correctly. These components, shown in Figure 16 form a loop

filter which integrates the current pulses from a charge pump

and produces a voltage which is used to tune the VCO. Good

quality capacitors, such as PPS film, are recommended .Figure

17 shows a block diagram of the PLL section including master

clock selection. Figure 18 shows how the clock frequencies at

the clock output pins, SYSCLK1-3 and the internal PLL clock

values, PLL1 and PLL2 are selected. The clock nodes, PLL1 and

PLL2, can be used as master clocks for the other blocks in the

ADAV802 such as the DAC or ADC. The PLL has separate

supply and ground pins and these should be as clean as possible

to prevent electrical noise being converted into clock jitter by

coupling onto the loop filter pins.

PLL

BLOCK

PLL_LFx

33nF

732

Ω

1.8nF

AVDD

Figure 16. PLL L

PHASE

DETECTOR

&LOOP

FILTER

VCO

N DIVIDER

OUTPUT

SCALER N1

REG: 0x74

BIT 4

REG: 0x74

BIT 5

PHASE

DETECTOR

&LOOP

FILTER

VCO

N DIVIDER

OUTPUT

SCALER N2

OUTPUT

SCALER N3

XIN

XOUT

MCLKI

MCLKO

PLL1

PLL2

PLL_LF1

PLL_LF2

SYSCLK1

SYSCLK2

SYSCLK3

REG: 0x78

BIT 6

REG: 0x78

BIT 7

801-0015

Figure

17. PLL Section Block Diagram

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