ADAV802_15 datasheet(3/53 Pages) AD

3 / 53 page

Preliminary Technical Data

ADAV802

Rev. Pr G | Page 3 of 53

SPECIFICATIONS

Table 1. Test Conditions Unless Otherwise Noted

Supply Voltage

Analog

+3.3 V

Digital

+3.3 V

Ambient Temperature

25°C

Master Clock (XIN)

12.288 MHz

Measurement Bandwidth

20 Hz to 20 kHz

Word Width (All Converters)

24-bits

Load Capacitance on Digital Outputs

100 pF

ADC Input Frequency

997Hz at −1 dBFS

DAC Output Frequency

997Hz at −1 dBFS

Digital Input: Slave Mode, I2S Justified Format

Digital Output: Master Mode, I2S Justified Forma

Table 2. PGA Section

Min

Typ

Max

Unit

Conditions

Input Impedance

Ω

Minimum Gain

Maximum Gain

Gain Step

0.5

Gain Step Error

TBD

Table 3. Reference Section

Min

Typ

Max

Unit

Conditions

Absolute Voltage, VREF

1.5

VREFTemperature Coefficient

TBD

ppm/

°C

Table 4. ADC Section1

Min

Typ

Max

Unit

Conditions

Number of Channels

Resolution

Bits

Dynamic Range

−60 dB Input

Unweighted

100

A-Weighted

102

Total Harmonic Distorton + Noise

−85

Input = −1.0 dBFS

Analog Input

Input Range (± Full Scale)

1.0

VRMS

VREF

1.5

DC Accuracy

Gain Error

−1

Interchannel Gain Mismatch

0.01

Gain Drift

100

ppm/°C

Offset

TBD

Crosstalk (EIAJ Method)

100

Volume Control Step Size (256 Steps)

0.39

% per step

Maximum Volume Attenuation

-48

Group Delay

TBD

µS

1 The figures quoted are target specifications and subject to change before release

ADAV802 Datasheet(PDF) 3 Page - Analog Devices

ADAV802 Datasheet(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL