ADAV802_15 datasheet(43/53 Pages) AD

43 / 53 page

Preliminary Technical Data

ADAV802

Rev. Pr G | Page 43 of 53

Table 66. DAC Control Register 1

DR_ALL

DR_DIG

CHSEL1

CHSEL0

POL1

POL0

MUTER

MUTEL

ADDRESS = 1100100

DR_ALL

Hard Reset and Powerdown

0 = Normal, Output pins go to VREF Level

1 = Hard Reset & Low Power, Output pins go to AGND

DR_ALL

DAC Digital Reset

0 = Normal

1 = Reset All except registers

CHSEL1-0

DAC Channel Select

00 = Normal Left-Right

01 = Both Right

10 = Both Left

11 = Swapped, Right-Left

POL1-0

DAC Channel Polarity

00 = Both Positive

01 = Left Negative

10 = Right Negative

11 = Both Negative

MUTER

Mute Right Channel

0 = Normal

1 = Mute

MUTEL

Mute Left Channel

0 = Normal

1 = Mute

Table 67. DAC Control Register 2

RES

DMCLK1

DMCLK0

DFS

DFS0

DEEM1

DEEM0

ADDRESS = 1100101

DMCLK1-0

DAC MCLK Divider

00 = MCLK

01 = MCLK/1.5

10 = MCLK/2

11 = MCLK/3

DFS1-0

DAC Interpolator Select

00 = 8 × (MCLK = 256 × fS)

01 = 4 × (MCLK = 128 × fS)

10 = 2 × (MCLK = 64 × fS)

11 = Reserved

DEEM1-0

DAC De-emphasis Select 00 = None

01 = 44.1 kHz

10 = 32 kHz

11 = 48 kHz

ADAV802 Datasheet(PDF) 43 Page - Analog Devices

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