ADAV802_15 datasheet(37/53 Pages) AD

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Preliminary Technical Data

ADAV802

Rev. Pr G | Page 37 of 53

Table 49. Receiver Error Mask Register

NonAudio

CRC

BiPhase/

RxValidity

Emphasis

Nonaudio

Preamble

Error

Nostream

Parity

Lock

Mask

ADDRESS = 0011001

RxValidity Mask

Masks the RxValidity bit from generating an interrupt

0= The RxValidity bit will not generate an interrupt

1 = The RxVvalidity bit will generate and interrupt

Emphasis Mask

Masks the Emphasis bit from generating an interrupt

0 = The Emphasis bit will not generate an interrupt

1 = The Emphasis bit will generate and interrupt

NonAudio Mask

Masks the NonAudio bit from generating an interrupt

0 = The NonAudio bit will not generate an interrupt

1 = The NonAudio bit will generate and interrupt

NonAudioPreamble

Mask

Masks the NonAudio Preamble bit from generating an interrupt

0 = The NonAudio Preamble bit will not generate an interrupt

1 = The NonAudio Preamble bit will generate and interrupt

CRCError Mask

Masks the CRC Error bit from generating an interrupt

0 = The CRC Error bit will not generate an interrupt

1 = The CRC Error bit will generate and interrupt

NoStream Mask

Masks the NoStream bit from generating an interrupt

0 = The NoStream bit will not generate an interrupt

1 = The NoStream bit will generate an interrupt

BiPhase/Parity Mask

Masks the BiPhase/Parity bit from generating an interrupt

0 = The BiPhase/Parity bit will not generate an interrupt

1 = The BiPhase/Parity bit will generate an interrupt

Lock Mask

Masks the Lock bit from generating an interrupt

0 = The Lock bit will not generate an interrupt

1 = The Lock bit will generate an interrupt

Table 50. Sample Rate Converter Error Register (Read Only)

RES

TOO_SLOW

OVRL

OVRR

MUTE_IND

ADDRESS = 0011010

TOO_SLOW

This bit is set when the clock to the SRC is too slow, i.e. there are not enough clock cycles to complete the internal

convolution.

OVRL

This bit will be set when the Left Output Data of the sample rate converter has gone over the full-scale range and has

been clipped. This bit will not be cleared until the register is read.

OVRR

This bit will be set when the Right Output Data of the sample rate converter has gone over the full-scale range and has

been clipped. This bit will not be cleared until the register is read.

MUTE_IND

Mute Indicated. This bit is set when the SRC is in Fast Mode and clicks or pops may be heard in the SRC output data. The

output of the SRC can be muted, if required, until the SRC is in Slow Mode. Once read this bit will remain in its state and

not generate an interrupt until it has changed state.

ADAV802 Datasheet(PDF) 37 Page - Analog Devices

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