ADAV802_15 datasheet(50/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 50 of 53

Table 85. Internal Clocking Control Register 2

RES

ICLK1-1

ICLK1-0

PLL2INT1

PLL2INT0

PLL1INT

ADDRESS = 1110111

ICLK1-0

Source Selector for Internal Clock ICLK1

00 = XIN

01 = MCLKI

10 = PLLINT1

11 = PLLINT2

PLL2INT1-0

PLL2 Internal Selector (See Figure 18)

00 = FS2

01 = FS2/2

10 = FS3

11 = FS3/2

PLL1INT

PLL1 Internal Selector

0 = FS1

1 = FS1/2

Table 86. PLL Clock Source Register

PLL1_Source

PLL2_Source

RES

ADDRESS = 1111000

PLL1_Source

Selects the clock source for PLL1

0 = XIN

1 = MCLKI

PLL2_Source

Selects the clock source for PLL2

0 = XIN

1 = MCLKI

Table 87. PLL Output Enable Register

RES

DIRIN_PIN

RES

SYSCLK1

SYSCLK2

SYSCLK3

ADDRESS = 1111010

DIRIN_PIN

This bit determines the input levels of the DIRIN pin

0 = The DIRIN will accept input signals down to 200mV according to AES3 requirements

1 = The DIRIN will accept input signals as defined in Table 13

SYSCLK1

Enables the SYSCLK1 Output

0 = Enabled

1 = Disabled

SYSCLK2

Enables the SYSCLK2 Output

0 = Enabled

1 = Disabled

SYSCLK3

Enables the SYSCLK3 Output

0 = Enabled

1 = Disabled

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