ADAV802_15 datasheet(47/53 Pages) AD

47 / 53 page

Preliminary Technical Data

ADAV802

Rev. Pr G | Page 47 of 53

Table 79. ADC Right Volume Register

AVOLR7

AVOLR6

AVOLR5

AVOLR4

AVOLR3

AVOLR2

AVOLR1

AVOLR0

ADDRESS = 1110001

AVOLR7-0

ADC Right Channel Volume Control

1111111 = 1.0 (0dBFS)

1111110 = 0.996 (-0.00348dBFS)

1000000 = 0.5 (-6dBFS)

0111111 = 0.496 (-6.09dBFS)

0000000 = 0.0039 (-48.18dBFS)

Table 80. ADC Left Peak Volume Register

RES

ALP5

ALP4

ALP3

ALP2

ALP1

ALP0

ADDRESS = 1110010

ALP5-0

ADC Left Channel Peak Volume Detection

000000 = 0dBFS

000001 = -1dBFS

111111 = -63dBFS

Table 81. ADC Right Peak Volume Register

RES

ARP5

ARP4

ARP3

ARP2

ARP1

ARP0

ADDRESS = 1110011

ARP5-0

ADC Right Channel Peak Volume Detection

000000 = 0dBFS

000001 = -1dBFS

111111 = -63dBFS

Table 82. PLL Control Register 1

RES

MCLKODIV

PLLDIV

PLL2PD

PLL1PD

XTLPD

SYSCLK3

ADDRESS = 1110100

MCLKODIV

Divide Input MCLK by 2 to generate MCLKO

0 = Disabled

1 = Enabled

PLLDIV

Divide XIN by 2 to generate the PLL master clock

0 = Disabled

1 = Enabled

PLL2PD

Powerdown PLL2

0 = Normal

1 = Powerdown

PLL1PD

Powerdown PLL1

0 = Normal

1 = Powerdown

XTLPD

Powerdown XTAL Oscillator

0 = Normal

1 = Powerdown

SYSCLK3

Clock Output for SYSCLK3

0 = 512 × fS

1 = 256 × fS

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