| Electronic Components Datasheet Search |
|
ADAV802 Datasheet(PDF) 9 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADAV802 Datasheet(HTML) 9 Page - Analog Devices |
|
9 / 53 page ![]() Preliminary Technical Data ADAV802 Rev. Pr G | Page 9 of 53 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ZEROL/INT ZEROR DVDD DGND ADVDD ADGND PLL_LF2 PLL_LF1 PLL_GND PLL_VDD DGND SYSCLK1 SYSCLK2 SYSCLK3 XIN XOUT 39 38 37 41 40 MCLKO MCLKI DVDD DGND 36 35 34 33 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 64 63 62 61 60 59 58 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) VINR VINL AGND AVDD DIR_LF DIR_GND DIR_VDD RESET CLATCH/AD0 CIN/SDA CCLK/SCL COUT/AD1 13 14 15 16 25 26 27 31 30 29 28 32 57 56 55 54 53 52 51 50 49 ADAV802 Figure 2. 64-Lead Plastic Quad Flatpack [LQFP] (ST-520) Table 18. ADAV802 Pin Function Descriptions Pin Number Input/Output Mnemonic Description 1 INPUT VINR Analog Audio Input - Right Channel 2 INPUT VINL Analog Audio Input - Left Channel 3 AGND Analog Ground 4 AVDD Analog Voltage Supply 5 DIR_LF DIR Phase Locked Loop (PLL) Loop Filter Pin 6 DIR_GND Supply Ground for DIR Analog Section. This pin should be connected to AGND 7 DIR_VDD Supply for DIR Analog Section. This pin should be connected to AVDD 8 INPUT RESET Reset input (Active Low) 9 INPUT CLATCH Chip Select (Control Latch) Pin of SPI compatible control interface 10 INPUT CIN Data Input of SPI compatible control interface 11 INPUT CCLK Clock Input of SPI compatible control interface 12 OUTPUT COUT Data Output of SPI compatible control interface 13 OUTPUT ZEROL/INT Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined by the INTRPT bin in DAC Control Register 4 14 OUTPUT ZEROR Right Channel (Output) Zero Flag 15 DVDD Digital Voltage Supply 16 DGND Digital Ground 17 INPUT/OUTPUT ILRCLK Sampling Clock (LRCLK) of Playback Digital Input Port 18 INPUT/OUTPUT IBCLK Serial Clock (BCLK) of Playback Digital Input Port 19 INPUT ISDATA Data Input of Playback Digital Input Port 20 INPUT/OUTPUT OLRCLK Sampling Clock (LRCLK) of Record Digital Output Port 21 INPUT/OUTPUT OBCLK Serial Clock (BCLK) of Record Digital Output Port 22 OUTPUT OSDATA Data Output of Record Digital Output Port |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |