ADAV802_15 datasheet(20/53 Pages) AD

20 / 53 page

ADAV802

Preliminary Technical Data

Rev. Pr G | Page 20 of 53

SYSCLK1

48 kHz

32 kHz

44.1 kHz

REG: 0x75

BIT 5

256

384

REG: 0x75

BITS 7-6

SYSCLK2

×2

REG: 0x75

BIT 4

REG: 0x77

BITS 2-1

PLLINT2

SYSCLK3

PLL1 MCLK

FS2

FS3

PLL2

PLL2 MCLK

48 kHz

32 kHz

44.1 kHz

REG: 0x75

BITS 3-2

256

384

REG: 0x75

BIT 1

×2

PLLINT1

REG: 0x75

BIT 0

REG: 0x77

BIT 0

FS1

PLL1

801-0016

REG: 0x74

BIT 0

256

512

Figure 18. PLL Clocking Scheme

SPDIF TRANSMITTER AND RECEIVER

The ADAV802 contains an integrated SPDIF transmitter and

receiver. The transmitter consists of a single output pin,

DITOUT, on which the biphase encoded data appears. The

SPDIF transmitter source can be selected from the different

blocks making up the ADAV802. Additionally the clock source

for the SPDIF transmitter can be selected from the various clock

sources available in the ADAV802. The receiver uses two pins,

DIRIN and DIR_LF. DIRIN accepts the SPDIF input data

stream. The DIRIN pin can be configured to accept a digital

input level as defined by Table 13 or an input signal with a peak

to peak level of 200mV minimum as defined by the IEC60958-3

specification. DIR_LF is a loop filter pin required by the

internal PLL which is used to recover the clock from the SPDIF

data stream. The components shown in Figure 22 form a loop

filter which integrates the current pulses from a charge pump

and produces a voltage which is used to tune the VCO of the

clock recovery PLL. The recovered audio data and audio clock

can be routed to the different blocks of the ADAV801 as

required. Figure 19 shows a conceptual diagram of the DIRIN

block.

LEVEL

DIRIN

SPDIF

RECEIVER

REG: 0x74

BIT 4

SPDIF

COMPARATOR

801-0128

1External Capacitor is only required for variable level SPDIF inputs

Figure 19. DIRIN Block

DIT

AUXILIARY IN

PLAYBACK

DIR

ADC

REG: 0x63

BITS 2-0

DIT

INPUT

SRC

DITOUT

Figure 20. Digital Output Transmitter Block Diagram

DIR

Audio

Data

DIRIN

Recovered

Clock

801-0022

Figure 21. Digital Input Receiver Block Diagram

ADAV802 Datasheet(PDF) 20 Page - Analog Devices

ADAV802 Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL