ADAV802_15 datasheet(32/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 32 of 53

Table 34. Receiver Configuration 2 Register

SP_PLL_

NO NON-

NO_

RxMUTE

SP-PLL

SEL1-0

RES

AUDIO

VALIDITY

5,4

ADDRESS = 0001010

RxMUTE

Hard Mutes the Audio Output for the AES3/SPDIF Receiver

0 = AES3/SPDIF Receiver is not muted

1 = AES3/SPDIF Receiver is muted

SP_PLL

The AES3/SPDIF Receiver PLL will accept a Left/Right Clock from one of the four serial ports as the PLL

reference clock

0 = Left/Right Clock generated from the AES3/SPDIF preambles is the reference clock to the PLL

1 = Left/Right Clock from one of the serial ports is the reference clock to the PLL

SP_PLL_SEL1-0 Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set

00 = Playback Port is selected

01 = Auxiliary Input Port is selected

10 = Record Port is selected

11 = Auxiliary Output Port is selected

NONAUDIO

When the NONAUDIO bit is set, data from the AES3/SPDIF Receiver will not be allowed into the Sample Rate

Converter (SRC). If the NONAUDIO data is due to DTS, AAC, etc. as defined by the IEC61937 standard, then the

data from the AES3/SPDIF Receiver will not be allowed into the SRC regardless of the state of this bit

0 = AES3/SPDIF Receiver data will be sent to the SRC

1 = Data fro the AES3/SPDIF Receiver will not be allowed into the SRC if the NONAUDIO bit is set

NO_VALIDITY

When the VALIDITY bit is set data from the AES3/SPDIF Receiver will not be allowed into the SRC

0 = AES3/SPDIF Receiver data will be sent to the SRC

1 = Data from the AES3/SPDIF Receiver will not be allowed into the SRC if the VALIDITY bit is set

Table 35. Receiver Buffer Configuration Register

RES

RxBCONF5

RxBCONF4

RxBCONF3

RxBCONF2-1

RxBCONF0

2,1

ADDRESS = 0001011

RxBCONF5

If the user bits are formatted according to the IEC60958-3 standard and the DAT Category is detected, the

User Bit interrupt is only enabled when there is a change in the Start (ID) bit.

0 = The User Bit interrupt is enabled in the normal mode.

1 = If the DAT category is detected, the User bit interrupt is only enabled if there is a change in the Start (ID)

bit

RxBCONF4

This bit determines whether Channel A and Channel B User Bits are stored in the buffer together or

separated between A and B

0 = The User Bits are stored together

1 = The User Bits are stored separately

RxBCONF3

Defines the function of RxCSBINT

0 = RxCSBINT will be set when a new block of receiver channel status is read, which is 192 audio frames

1 = RxCSBINT will be set only if the first five bytes of the receiver channel status block changes from the

previous channel status block

RxBCONF2-1

Defines the User Bit Buffer

00 = User Bits are ignored

01 = Update the second user bit buffer when the first user bit buffer is full

10 = Format the received user bits according to byte 1, bits 4-7, of the channel status if the PRO bit is set. If

the PRO bit is not set format the user bits according to the IEC60958-3 standard

11 = Reserved

RxBCONF0

Defines the User Bit buffer size if RxBCONF2-1 = 01

0 = 384 Bits with Preamble-Z as the start of the buffer

1 = 768 Bits with Preamble-Z as the start of the buffer

ADAV802 Datasheet(PDF) 32 Page - Analog Devices

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