ADAV802_15 datasheet(27/53 Pages) AD

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Preliminary Technical Data

ADAV802

Rev. Pr G | Page 27 of 53

CLATCH

CCLK

CIN

COUT

D15

D14

Figure 37. SPI Serial Port Timing Diaram

98765

43210

ADDRESS [6:0]

DATA [7:0]

Figure 38. SPI Control Word Format

Block Reads and Writes

The ADAV802 provides the user with the ability to write to or

read from a block of registers in one continuous operation. In

SPI mode, the CLATCH line should be held low for longer than

the 16 CCLK periods to use the block read/write mode. For a

write operation, once the LSB has been clocked into the

ADAV802, on the 16th CCLK the register address as specified

by the first 7 bits of the write operation is incremented and the

next 8 bits will be clocked into the next Register Address. The

read operation is similar. Once the LSB of a read register

operation has been clocked out the Register Address is

incremented and the data from the next register will be clocked

out on the following 8 CCLKs. Figure 39 and Figure 40 show the

timing diagrams for the block write and read operations.

W=0

8BITS

8 BITS

8BITS

CLATCH

CIN

Figure 39. SPI Block Write Operation

W=1

8BITS

8 BITS

8BITS

CLATCH

CIN

DON’T CARE

COUT

Figure 40. SPI Block Reade Operatio

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