ADAV802_15 datasheet(26/53 Pages) AD

26 / 53 page

ADAV802

Preliminary Technical Data

Rev. Pr G | Page 26 of 53

PLLINT1

PLLINT2

ICLK1

MCLKI

XIN

ICLK2

REG: 0x76

BITS 4-2

DIR PLL (512

× fS)

DIR PLL (256

× fS)

PLLINT1

PLLINT2

MCLKI

XIN

ADC

MCLK

OUTPUT

PORT

OLRCLK

OBCLK

OSDATA

DIR PLL (512

× fS)

DIR PLL (256

× fS)

PLLINT1

PLLINT2

MCLKI

XIN

REG: 0x76

BITS 7-5

DAC

MCLK

REG: 0x77

BITS 4-3

REG: 0x76

BITS 1-0

DIR PLL (512

× fS)

DIR PLL (256

× fS)

REG: 0x00

BIT 1-0

SRC

MCLK

INPUT

PORT

ILRCLK

IBCLK

ISDATA

ICLK1

ICLK2

PLL CLOCK

REG:0X04

BITS 4-3

ICLK1

ICLK2

REG:0x06

BITS 4-3

PLL CLOCK

MCLKI

XIN

PLLINT1

PLLINT2

Figure 34. Sport Clocking Scheme

ADC

SRC

DAC

PLAYBACK

DATA

INPUT

AUX

DATA

INPUT

DIR

DIT

AUX

DATA

OUTPUT

RECORD

DATA

OUTPUT

CONTROL

REGISTERS

REFERENCE

OSCILLATOR

PLL

Figure 35. Data Path

INTERFACE CONTROL

The ADAV802 has a dedicated control port to allow the internal

registers of the ADAV802 to be accessed. Each of the internal

registers is 8 bits wide. Where bits are described as reserved

(RES) these bits should be programmed as zero.

SPI Interface

Control of the ADAV802 is via an SPI compatible serial port.

The SPI control port is a 4 wire serial control port with one

cycle of data transfer consisting of 16 bits. Figure 36 shows the

format of an SPI write/read of the ADAV802. The transfer of

data is initiated on the falling edge of CLATCH. The data

presented on the first 7 CCLKs represents the register address

required to be written to or read from. The 8th bit of data is a

Read/Write bit. If this bit is low the following 8 bits of data will

be loaded to register address provided. If this bit is high a read

operation is indicated. The contents of the register address will

be clocked out on the COUT pin on the following 8 CCLKs. For

a read operation the data bits after the Read/Write bits are

ignored.

ADAV802 Datasheet(PDF) 26 Page - Analog Devices

ADAV802 Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL