ADAV802_15 datasheet(36/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 36 of 53

Table 46. Preamble-D MSB Register (Read Only)

PRE_D15-PRE_D08

7,6,5,4,3,2,1,0

ADDRESS = 0010110

PRE_D15-08

The eight most significant bits of the sixteen bit Preamble-D when Nonaudio data is detected according to the

IEC60937 standard, otherwise bits show zeros. When subframe Nonaudio is used this becomes the 8 most

significant bits of the 16 bit Preamble-C of Channel B

Table 47. Preamble-D LSB Register (Read Only)

PRE_D07-PRE_D00

7,6,5,4,3,2,1,0

ADDRESS = 0010111

PRE_D07-00

The eight least significant bits of the sixteen bit Preamble-D when Nonaudio data is detected according to

the IEC60937 standard, otherwise bits show zeros When subframe Nonaudio is used this becomes the 8 most

significant bits of the 16 bit Preamble-C of Channel B

Table 48. Receiver Error Register (Read Only)

Non-

NonAudio

CRC-

No-

BiPhase/

RxValidity

Emphasis

Audio

Preamble

Error

Stream

Parity

Lock

ADDRESS = 0011000

RxValidity

This is the VALIDITY bit in the AES3 Received stream

Emphasis

This bit will be set if the audio data is preemphasized. Once it has been read it will remain high and

not generate an interrupt unless it changes state

NonAudio

This bit will be set when Channel Status Bit 1 (Nonaudio) is set. Once it has been read it will not

generate another interrupt unless the data becomes audio or the type of nonaudio data changes

NonAudio Preamble

This bit will be set if the audio data is nonaudio due to the detection of a Preamble. The NonAudio

Preamble Type register will indicate what type of preamble was detected. Once read it will remain

in its state and not generate an interrupt unless it has changed state

CRCError

This bit is the error flag for the channel status CRC error check. This bit will not clear until the

Receiver Error Register is read

NoStream

This bit will be set if there is no AES3/SPDIF stream present at the AES3/SPDIF receiver. Once read it

will remain high and not generate an interrupt unless its changes state.

BiPhase/Parity

This bit will be set if a biphase or parity error occurred in the AES3/SPDIF stream. This bit will not be

cleared until the register is read.

Lock

This bit will be set if the PLL has locked or cleared when the PLL loses lock. Once read it will remain

in its state and not generate an interrupt unless it has changed state.

ADAV802 Datasheet(PDF) 36 Page - Analog Devices

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